Regression
simulation_libraries_msl32.Modelica.Electrical.Digital.Examples.FullAdder.mos (from (result.xml))
Stacktrace
Output mismatch (see stdout for details)
Standard Output
+ Modelica.Electrical.Digital.Examples.FullAdder ... execution failed ==== Log C:\Users\adrpo33\AppData\Local\Temp/omc-rtest-adrpo33/simulation/libraries/msl32/Modelica.Electrical.Digital.Examples.FullAdder.mos_temp7369/log-Modelica.Electrical.Digital.Examples.FullAdder.mos "true " "" OpenModelicaModelTesting.Kind.VerifiedSimulation Modelica.Electrical.Digital.Examples.FullAdder {"Enable.y","CLK.y","Counter.q0","Counter.q1","Counter.q2","Adder1.s","Adder1.c_out","s.y[1]","c_out.y[1]"} Alarm clock == 1 out of 1 tests failed [simulation/libraries/msl32/Modelica.Electrical.Digital.Examples.FullAdder.mos_temp7369, time: 483]