Regression

simulation_libraries_msl32.Modelica.Electrical.Digital.Examples.DLATREG.mos (from (result.xml))

Failing for the past 1 build (Since #3764 )

Took 8 min 2 sec.

Stacktrace

Output mismatch (see stdout for details)

Standard Output

 + Modelica.Electrical.Digital.Examples.DLATREG                                      ... execution failed

==== Log C:\Users\adrpo33\AppData\Local\Temp/omc-rtest-adrpo33/simulation/libraries/msl32/Modelica.Electrical.Digital.Examples.DLATREG.mos_temp1397/log-Modelica.Electrical.Digital.Examples.DLATREG.mos
"true
"
""
OpenModelicaModelTesting.Kind.VerifiedSimulation
Modelica.Electrical.Digital.Examples.DLATREG
{"data_1.y","data_0.y","enable.y","reset.y","dLATREG.dataOut[1]","dLATREG.dataOut[2]"}
Alarm clock
== 1 out of 1 tests failed [simulation/libraries/msl32/Modelica.Electrical.Digital.Examples.DLATREG.mos_temp1397, time: 482]