Regression
simulation_libraries_msl32.Modelica.Electrical.Digital.Examples.Adder4.mos (from (result.xml))
Stacktrace
Output mismatch (see stdout for details)
Standard Output
+ Modelica.Electrical.Digital.Examples.Adder4 ... execution failed ==== Log C:\Windows\TEMP/omc-rtest-OpenModelica/simulation/libraries/msl32/Modelica.Electrical.Digital.Examples.Adder4.mos_temp4887/log-Modelica.Electrical.Digital.Examples.Adder4.mos "true " "" OpenModelicaModelTesting.Kind.VerifiedSimulation Modelica.Electrical.Digital.Examples.Adder4 {"a1.y","b1.y","a2.y","b2.y","a3.y","b3.y","a4.y","b4.y","Set.y","Adder1.s","Adder1.c_out","Adder2.s","Adder2.c_out","Adder3.s","Adder3.c_out","Adder4.s","Adder4.c_out"} Alarm clock == 1 out of 1 tests failed [simulation/libraries/msl32/Modelica.Electrical.Digital.Examples.Adder4.mos_temp4887, time: 483]