Regression
simulation_libraries_msl32.Modelica.Electrical.Digital.Examples.DFFREG.mos (from (result.xml))
Stacktrace
Output mismatch (see stdout for details)
Standard Output
+ Modelica.Electrical.Digital.Examples.DFFREG ... execution failed ==== Log C:\Windows\TEMP/omc-rtest-OpenModelica/simulation/libraries/msl32/Modelica.Electrical.Digital.Examples.DFFREG.mos_temp2808/log-Modelica.Electrical.Digital.Examples.DFFREG.mos "true " "" OpenModelicaModelTesting.Kind.VerifiedSimulation Modelica.Electrical.Digital.Examples.DFFREG {"dFFREG.reset","dFFREG.clock","dFFREG.dataIn[1]","dFFREG.dataIn[2]","dFFREG.dataOut[1]","dFFREG.dataOut[2]"} Alarm clock == 1 out of 1 tests failed [simulation/libraries/msl32/Modelica.Electrical.Digital.Examples.DFFREG.mos_temp2808, time: 482]