Regression
simulation_libraries_msl32.Modelica.Electrical.Digital.Examples.DFFREGSRH.mos (from (result.xml))
Stacktrace
Output mismatch (see stdout for details)
Standard Output
+ Modelica.Electrical.Digital.Examples.DFFREGSRH ... execution failed ==== Log C:\WINDOWS\TEMP/omc-rtest-OpenModelica/simulation/libraries/msl32/Modelica.Electrical.Digital.Examples.DFFREGSRH.mos_temp6848/log-Modelica.Electrical.Digital.Examples.DFFREGSRH.mos "true " "" OpenModelicaModelTesting.Kind.VerifiedSimulation Modelica.Electrical.Digital.Examples.DFFREGSRH {"set.y","data_1.y","data_0.y","clock.y","reset.y","dFFREGSRH.dataOut[1]","dFFREGSRH.dataOut[2]"} Alarm clock == 1 out of 1 tests failed [simulation/libraries/msl32/Modelica.Electrical.Digital.Examples.DFFREGSRH.mos_temp6848, time: 483]