Regression
simulation_libraries_msl32.Modelica.Electrical.Analog.Examples.ShowVariableResistor.mos (from (result.xml))
Stacktrace
Output mismatch (see stdout for details)
Standard Output
+ Modelica.Electrical.Analog.Examples.ShowVariableResistor ... execution failed ==== Log C:\Windows\TEMP/omc-rtest-OpenModelica/simulation/libraries/msl32/Modelica.Electrical.Analog.Examples.ShowVariableResistor.mos_temp205/log-Modelica.Electrical.Analog.Examples.ShowVariableResistor.mos "true " "" OpenModelicaModelTesting.Kind.VerifiedSimulation Modelica.Electrical.Analog.Examples.ShowVariableResistor {"R1.i","R1.v","R4.i","R4.v"} Alarm clock == 1 out of 1 tests failed [simulation/libraries/msl32/Modelica.Electrical.Analog.Examples.ShowVariableResistor.mos_temp205, time: 482]