Regression
simulation_libraries_msl32.Modelica.Electrical.Digital.Examples.DLATREGSRL.mos (from (result.xml))
Stacktrace
Output mismatch (see stdout for details)
Standard Output
+ Modelica.Electrical.Digital.Examples.DLATREGSRL ... execution failed ==== Log C:\Windows\TEMP/omc-rtest-OpenModelica/simulation/libraries/msl32/Modelica.Electrical.Digital.Examples.DLATREGSRL.mos_temp2108/log-Modelica.Electrical.Digital.Examples.DLATREGSRL.mos "true " "" OpenModelicaModelTesting.Kind.VerifiedSimulation Modelica.Electrical.Digital.Examples.DLATREGSRL {"set.y","data_1.y","data_0.y","enable.y","reset.y","dLATREGSRL.dataOut[1]","dLATREGSRL.dataOut[2]"} Alarm clock == 1 out of 1 tests failed [simulation/libraries/msl32/Modelica.Electrical.Digital.Examples.DLATREGSRL.mos_temp2108, time: 483]