Failed

tests / testsuite-clang / simulation_libraries_msl32.Modelica.Electrical.Digital.Examples.RAM.mos (from (result.xml))

Failing for the past 9 builds (Since #16 )

Took 1 sec.

Stacktrace

Output mismatch (see stdout for details)

Standard Output

 + Modelica.Electrical.Digital.Examples.RAM                                          ... execution failed

==== Log /tmp/omc-rtest-unknown/simulation/libraries/msl32/Modelica.Electrical.Digital.Examples.RAM.mos_temp9448/log-Modelica.Electrical.Digital.Examples.RAM.mos
"true
"
""
OpenModelicaModelTesting.Kind.VerifiedSimulation
Modelica.Electrical.Digital.Examples.RAM
{"addr_1.y","addr_0.y","data_1.y","data_0.y","RE.y","WE.y","dLATRAM.dataOut[1]","dLATRAM.dataOut[2]"}
loadModel(Modelica,3.2.1)
/var/lib/jenkins/workspace/OpenModelica_maintenance_v1.13/testsuite/simulation/libraries/msl32/Modelica.Electrical.Digital.Examples.RAM.mos_temp9448

== 1 out of 1 tests failed [simulation/libraries/msl32/Modelica.Electrical.Digital.Examples.RAM.mos_temp9448, time: 1]