Regression
simulation_libraries_msl32.Modelica.Electrical.Analog.Examples.IdealTriacCircuit.mos (from (result.xml))
Stacktrace
Output mismatch (see stdout for details)
Standard Output
+ Modelica.Electrical.Analog.Examples.IdealTriacCircuit ... execution failed ==== Log C:\Users\adrpo33\AppData\Local\Temp/omc-rtest-adrpo33/simulation/libraries/msl32/Modelica.Electrical.Analog.Examples.IdealTriacCircuit.mos_temp870/log-Modelica.Electrical.Analog.Examples.IdealTriacCircuit.mos "true " "" OpenModelicaModelTesting.Kind.VerifiedSimulation Modelica.Electrical.Analog.Examples.IdealTriacCircuit {"idealTriac.capacitor.v"} Alarm clock == 1 out of 1 tests failed [simulation/libraries/msl32/Modelica.Electrical.Analog.Examples.IdealTriacCircuit.mos_temp870, time: 482]