Regression
simulation_libraries_msl32.Modelica.Electrical.Analog.Examples.CharacteristicIdealDiodes.mos (from (result.xml))
Stacktrace
Output mismatch (see stdout for details)
Standard Output
+ Modelica.Electrical.Analog.Examples.CharacteristicIdealDiodes ... execution failed ==== Log C:\Users\adrpo33\AppData\Local\Temp/omc-rtest-adrpo33/simulation/libraries/msl32/Modelica.Electrical.Analog.Examples.CharacteristicIdealDiodes.mos_temp7574/log-Modelica.Electrical.Analog.Examples.CharacteristicIdealDiodes.mos "true " "" OpenModelicaModelTesting.Kind.VerifiedSimulation Modelica.Electrical.Analog.Examples.CharacteristicIdealDiodes {"R1.i","R1.v","R2.i","R2.v","R3.i","R3.v"} Alarm clock == 1 out of 1 tests failed [simulation/libraries/msl32/Modelica.Electrical.Analog.Examples.CharacteristicIdealDiodes.mos_temp7574, time: 482]