Regression
simulation_libraries_msl32.Modelica.Electrical.Analog.Examples.AD_DA_conversion.mos (from (result.xml))
Stacktrace
Output mismatch (see stdout for details)
Standard Output
+ Modelica.Electrical.Analog.Examples.AD_DA_conversion ... execution failed ==== Log C:\Users\adrpo33\AppData\Local\Temp/omc-rtest-adrpo33/simulation/libraries/msl32/Modelica.Electrical.Analog.Examples.AD_DA_conversion.mos_temp7946/log-Modelica.Electrical.Analog.Examples.AD_DA_conversion.mos "true " "" OpenModelicaModelTesting.Kind.VerifiedSimulation Modelica.Electrical.Analog.Examples.AD_DA_conversion {"pulse.y","sineVoltage.v","sineVoltage.i","resistor.v"} Alarm clock == 1 out of 1 tests failed [simulation/libraries/msl32/Modelica.Electrical.Analog.Examples.AD_DA_conversion.mos_temp7946, time: 482]